1. Field of the Invention
The present disclosure generally relates to methods for fabricating integrated circuits, and, more particularly, to methods for fabricating integrated circuits with improved spacers.
2. Description of the Related Art
The ongoing trend in electronics towards more and more complex integrated circuits requires the dimensions of electronic devices to decrease in order to achieve a higher and higher integration density.
Transistors are the dominant circuit elements in current integrated circuits. Currently, several hundred millions of transistors may be provided in presently available complex integrated circuits, such as microprocessors, CPUs, storage chips and the like. It is then crucial that the typical dimensions of the transistors included in an integrated circuit are as small as possible, so as to enable a high integration density.
Among the various fabrication technologies of integrated circuits, the MOS (metal-oxide-semiconductor) technology is currently the most promising approach, since it enables producing devices with superior characteristics in terms of operating speed, power consumption and cost efficiency. The CMOS (complementary metal-oxide-semiconductor) technology is a particular implementation of the MOS technology wherein pairs of complementary transistors, i.e., P-channel transistors and N-channel transistors grouped in pairs, are used for forming circuit elements, such as inverters and other logic gates to design highly complex circuit assemblies. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed in active regions defined within a semiconductor layer supported by a substrate.
Presently, the layer in which most integrated circuits are formed is made out of silicon, which may be provided in crystalline, polycrystalline or amorphous form. Other materials such as, for example, dopant atoms or ions may be introduced into the original semiconductor layer.
A MOS transistor or generally a field-effect transistor (FET), irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises a source and a drain region, highly doped with dopants of the same species. An inversely or weakly doped channel region is then arranged between the drain and the source regions. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, may be controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region depends on, among other things, the mobility of the charge carriers and on the distance along the transistor width direction between the source and drain regions, which is also referred to as channel length. For example, by reducing the channel length, the channel resistivity decreases. Thus, an increased switching speed and higher drive current capabilities of a transistor may be achieved by decreasing the transistor channel length.
However, reduction of transistor channel length may not be pushed to extreme limits without incurring other problems. For example, the capacitance between the gate electrode and the channel decreases with decreasing channel length. This effect must then be compensated for by reducing the thickness of the insulating layer between the gate and the channel. For example, for a gate length of approximately 80 nm, a gate dielectric material based on silicon dioxide with a thickness of less than 2 nm may be required in high speed transistor elements. Such small thicknesses of the insulating might, however, result in increased leakage currents caused by hot carrier injection and direct tunneling of charge carriers through the extremely thin gate dielectric material. Since a further reduction in thickness of silicon dioxide-based gate dielectric materials may increasingly become incompatible with thermal power requirements of sophisticated integrated circuits, other alternatives have been developed in order to increase the charge carrier mobility in the channel region, thereby also enhancing overall performance of field effect transistors.
One of the solutions found to the problem of the increased capacitance with reduction of transistor channel length consists of choosing an appropriate material for the insulating layer in the gate electrode. When fabricating transistors with typical gate dimensions below 50 nm, the so-called “high-k/metal gate” (HKMG) technology has by now become the new manufacturing standard. According to the HKMG manufacturing process flow, the insulating layer included in the gate electrode is comprised of a high-k material. This is in contrast to the conventional oxide/polysilicon (poly/SiON) method, whereby the gate electrode insulating layer is typically comprised of an oxide, preferably silicon dioxide or silicon oxynitride in the case of silicon-based devices. By high-k material it is referred to a material with a dielectric constant “k” higher than 10. Examples of high-k materials used as insulating layers in gate electrodes are tantalum oxide (Ta2O5), strontium titanium oxide (SrTiO3), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), zirconium oxide (ZrO2) and the like.
HKMG enables increasing the thickness of the insulation layer in the gate electrode, thereby significantly reducing leakage currents through the gate, even at transistor channel lengths as low as 30 nm or smaller. However, implementation of HKMG brings about new technological challenges and requires new integration schemes with respect to the conventional poly/SiON technology.
For example, it has been found that when using hafnium oxide (HfO2) as the insulating layer material in a transistor gate, an interaction of the insulating layer material with polycrystalline silicon also present in the gate takes place, resulting in a variety of issues such as a high threshold voltage of the transistor. Thus, new materials have to be found in order to tune the work function of gate electrode species, so as to adjust the transistor threshold voltage to a desired level. A thin “work function metal” layer is inserted for this purpose between the high-k dielectric and the gate material, typically polycrystalline silicon, placed above the high-k dielectric. The threshold voltage may thus be adjusted by varying the thickness of the metal layer. This gate metal layer typically comprises a titanium nitride (TiN) film, possibly in conjunction with a work function metal, such as aluminum.
Currently, two different schemes exist for implementing HKMG in the semiconductor fabrication process flow. In the first approach, called gate-first, the fabrication process flow is similar to that followed during the traditional poly/SiON method. Formation of the gate electrode, including the high-k dielectric film and the work function metal film, is initially performed, followed by the subsequent stages of transistor fabrication, e.g., definition of source and drain regions, silicidation of portions of the substrate surface, metallization, etc. On the other hand, according to the second scheme, also known as gate-last or replacement gate, fabrication stages, such as dopant ion implantation, source and drain region formation and substrate silicidation, are performed in the presence of a sacrificial dummy gate. The dummy gate is replaced by the real gate after the high-temperature source/drain formation and all silicide annealing cycles have been carried out.
Thus, the gate-first HKMG approach requires the gate electrode stack to withstand the high temperatures reached during the annealing steps performed in order to, e.g., activate the dopant species implanted in the source and drain regions or induce the silicidation process.
Furthermore, oxygen or other gaseous contaminants might likely diffuse into the gate insulation layer or the gate metal layer during the thermal budget undergone by the device. Oxygen diffusion is particularly fast at the typically high temperatures reached during the thermal budget. Oxygen or contaminant incorporation into the gate stack during device fabrication should be prevented from occurring, since this has been observed to vary the chemical and physical characteristics of the materials included in the gate structure in an undesirable manner. Thus, crucial features of the transistor to be fabricated, such as the threshold voltage, might not be defined in advance.
One more factor which could jeopardize the integrity of the gate stack during the fabrication process is provided by the series of wet or dry etches performed after gate formation in order to pattern or clean the device surface. Ideally, the gate stack should be unaffected by all patterning or surface cleaning processes carried out after gate stack formation.
Thus, in order to protect the sensitive gate materials during the subsequent fabrication stages, the gate stack is encapsulated into a dielectric casing formed on its sidewall. This protective layer, also known as “spacer” or “spacer structure,” besides protecting the sensitive gate materials, is advantageously used as a mask when implanting dopants of a desired type into the semiconductor layer in which the transistor is formed. In this respect, the spacer structure may be formed in subsequent stages so as to have the appropriate shape and thickness during each implantation step.
In particular, the spacer structure may be comprised of an encapsulating portion formed adjacent to the stack sidewalls. A first spacer portion having a first thickness is then formed onto the encapsulating portion. This first portion is usually called “spacer-0.” A first series of implantations may be performed using the spacer-0 as a mask. This first series may include implantations carried out in order to define halo regions in the transistor channel region and extension regions in the source and drain regions. Subsequently, the spacer structure may be broadened by forming a second portion onto the spacer-0 previously formed. This second portion is usually referred to as “spacer-1.” A second series of implantations may then be performed in the presence of both spacer-0 and spacer-1, for example in order to define the deep regions of the source and drain regions.
According to the state of the art, the gate-encapsulating portion and spacer-0 are formed by using a two-stage process. The gate-encapsulating portion is initially formed at a first temperature by performing a first deposition step. Deposition of the gate-encapsulating portion is then followed by the formation of spacer-0, which exposes a surface to the outside. Spacer-0 is formed by carrying out a second deposition at a second temperature, which is usually higher than the first temperature. The entire process will be discussed more extensively in the following.
FIGS. 1a-1g illustrate some aspects of a typical process flow during fabrication of a FET according to the prior art. FIG. 1a schematically illustrates a cross-sectional view of a semiconductor structure 100 in a relatively advanced manufacturing stage. As shown, the semiconductor structure 100 comprises a substrate 101, such as a semiconductor material and the like, above which a semiconductor layer 102 is formed.
The semiconductor layer 102 is typically made of a silicon single crystal. The semiconductor layer 102 is laterally divided into a plurality of active regions 102a, which are to be understood as semiconductor regions in and above which one or more transistors are to be formed. For convenience, a single active region 102a is illustrated, which is laterally delimited by an isolation region 102b, such as a shallow trench isolation. Depending on the overall device requirements, the substrate 101 and the semiconductor layer 102, for instance initially provided as a silicon material, may form an SOI (silicon-on-insulator) architecture when a buried insulating material (not shown) is formed directly below the semiconductor layer 102. In other cases, initially the semiconductor layer 102 represents a part of the crystalline material of the substrate 101 when a bulk configuration is to be used for the semiconductor structure 100.
The semiconductor structure 100 includes a transistor 150 formed in and above active region 102a. FIG. 1a shows transistor 150, which can be a FET, during a fabrication stage following the formation of a gate electrode structure 160.
The gate structure 160 comprises gate electrode material 162, which may be comprised of polycrystalline silicon. The gate structure 160 further comprises an insulation layer 161 physically and electrically separating gate electrode material 162 from the transistor channel region to be formed in active region 102a. The gate electrode structure 160 may have any appropriate geometric configuration, for instance in terms of length and width. For example, the gate length, i.e., in FIG. 1a, the horizontal extension of electrode material 162, may be 50 nm or less.
Depending on the configuration of the gate electrode structure 160, insulation layer 161 and gate electrode material 162 may be formed in different ways.
For example, if the gate electrode 160 is a conventional oxide/polysilicon gate electrode (e.g., poly/SiON), then the gate insulation layer 161 may be formed from a conventional gate dielectric material, such as, for example, silicon dioxide, silicon oxynitride, and the like, whereas the gate electrode material 162 may comprise polysilicon.
Alternatively, an HKMG configuration may be preferred for gate electrode structure 160. HKMG is usually preferred for gate lengths of about 50 nm or smaller. In this case, the insulation layer 161 may be one of the high-k gate dielectric materials well known in the art. For example, a non-exhaustive list of high-k materials which may be used in transistor gates has been given above.
If the gate electrode structure 160 has been formed according to the HKMG technology, it also comprises a gate metal layer 162a, for instance in the form of tantalum nitride and the like, possibly in combination with a work function metal species, such as aluminum and the like. The gate metal layer 162a is typically formed above the insulation layer 161, thereby adjusting an appropriate work function and thus threshold voltage of the transistor 150, as discussed above.
As said above, in order to protect the stack of which gate electrode structure 160 is comprised, a spacer structure is formed on the sidewalls of the gate stack. The spacer structure is initially formed with a smaller thickness and subsequently broadened to a larger thickness.
FIGS. 1b-1d show a sequence of manufacturing stages resulting in the formation of the portion of the spacer structure comprising the encapsulating portion adjacent to the gate stack and an outer layer having a predetermined thickness, commonly called spacer-0.
As shown in FIG. 1b, during the initial stage of spacer formation, a deposition process 182 is performed so as to form a first insulating layer 144 on the surface of the semiconductor structure 100. The first insulating layer 144 is typically comprised of an insulating material such as, for example, silicon nitride (SiN). The layer 144 typically has a thickness between 3-4 nm and, preferably, of about 3.5 nm. The layer 144, formed so as to be in contact with the gate structure 160, is adapted to be patterned in order to form the encapsulating portion of the spacer structure.
The deposition process 182 used for forming the first insulating layer 144 is typically performed by means of an atomic layer deposition (ALD) process. The sequence of operations making up deposition 182 is schematically illustrated by broken line 482 in the plot of temperature as a function of time shown in FIG. 4a. Segment 482a indicates a boat push at 250° C. into the ALD furnace. The temperature is then ramped up to 500° C. during segment 482b. ALD deposition is performed thereafter at 500° C. during segment 482c of line 482. ALD deposition is indicated as a full rectangle 482dep in FIG. 4a. After performing ALD deposition 482dep, boat pull 482pull is carried out at 500° C.
The relatively low temperatures of 250° C. for boat push and of 500° C. for ALD are chosen when performing deposition 182 since they effectively prevent residual oxygen in the deposition chamber from reaching the gate stack 160. Once the gate stack 160 has been encapsulated by layer 144, it may endure higher temperatures in subsequent steps.
We now refer to FIG. 1c, showing semiconductor structure 100 during a fabrication stage following that shown in FIG. 1b. After depositing the first insulating layer 144, a second insulating layer 146 may be deposited by using a second deposition process 184. The second insulating layer 146 is deposited onto the surface of the first insulating layer 144. Usually, the second insulating layer 146 comprises the same insulating material as the first insulating layer 144. Thus, the second insulating layer 146 is typically comprised of SiN. The layer 146 has a thickness in the range of 8-9 nm and, preferably, of about 8.5 nm. The second insulating layer 146, formed onto the first insulating layer 144, is adapted to be patterned in order to form the portion of the spacer structure called spacer-0.
The deposition process 184 used for forming the second insulating layer 146 is typically performed by a low pressure chemical vapor deposition (LPCVD) process. This deposition process is schematically illustrated as a broken line 484 in the temperature versus process time plot shown in FIG. 4b. Segment 484a indicates a boat push at 700° C. into the LPCVD furnace. As shown by segment 484b, the temperature is then ramped up to 750° C. The deposition of layer 146, indicated as a full rectangle, is achieved by an LPCVD process at 750° C. during segment 484c. As indicated by segment 484d, the temperature is then decreased down to 700° C. and, finally, boat pull is performed at 700° C. in segment 484e. 
The temperature of 750° C. during LPCVD of the second insulating layer 146 allows for formation of a spacer-0 with improved toughness. In particular, a spacer-0 formed from an insulating layer 146 grown by means of an LPCVD performed at the selected temperature turns out to have an extremely low etch rate when exposed to typical wet etches applied to the wafer after spacer-0 has been formed.
We now refer to FIG. 1d, showing the semiconductor structure 100 during a fabrication stage following that shown in FIG. 1c. After forming the first insulating layer 144 and second insulating layer 146, layers 144 and 146 may be patterned in order to remove those portions not lying in the proximity of the gate structure 160. In particular, one or more dry or wet etches may be used in order to pattern layers 144 and 146. The patterning step results in the formation of a spacer structure 140 comprising an encapsulating portion 144enc formed adjacent to the sidewalls of the gate structure 160. The encapsulating portion 144enc of spacer structure 140 has been obtained as a portion of the patterned first insulating layer 144. In the stage of the manufacturing process flow shown in FIG. 1d, the spacer structure 140 further comprises an outer portion 146sp0 exposed to the outside and obtained as a portion of the patterned second insulating layer 146. The outer portion 146sp0 forms the portion of the spacer structure 140 called spacer-0.
After forming the spacer structure 140 as shown in FIG. 1d, a series of doping implantations 188 may be performed in order to define extension regions and/or halo regions. The implantations 188 may comprise halo implantations and/or implantations performed in order to define extension regions 151e of source and drain regions 151. FIG. 1e shows the transistor 150 after performing the implantations 188 resulting in the formation of extension regions 151e of the source and drain regions. The extension regions 151e determine the length of the channel region of the transistor 150.
FIG. 1f shows the semiconductor structure 100 during a fabrication stage following that shown in FIG. 1e. After performing halo and/or extension region implantations, a third insulating layer, not shown in the figures, may be deposited by using a highly conformal deposition technique. This third insulating layer may be patterned so as to form the portion 148 of spacer structure 140 called spacer-1.
After broadening the spacer structure 140 by forming spacer-1 148, further implantation steps (not shown) may be performed in order to define deep regions 151d of source and drain regions 151. The semiconductor structure 100 may subsequently be annealed in order to activate the implanted dopants and cause the crystal lattice of semiconductor layer to re-crystallize after implantation damage. A certain amount of diffusion of the doping species may likely result from application of the annealing process. The channel region 155 of transistor 150 is defined as being delimited by extension regions 151e. Figure if schematically shows the semiconductor structure 100 after the activating annealing has been performed.
FIG. 1g shows the semiconductor structure 100 during an advanced stage of the manufacturing process flow following that shown in FIG. 1f. After performing the activating annealing, a refractory metal layer (not shown) is deposited onto the surface of device 100 shown in FIG. 1f, after the gate electrode structure 160 has been formed and source and drain regions 151 have been created. A heat treatment is then applied to the refractory metal layer at temperatures ranging from 300-500° C. As a result of the heat treatment, metal silicide layer 162b shown in FIG. 1g is formed partly in and partly on top of the upper surface of the gate electrode material 162, which was exposed before depositing the refractory metal layer. Analogously, a metal silicide layer 153 is formed partly in and partly on top of the upper surface of the semiconductor layer 102, which was exposed before depositing the refractory metal layer.
After forming metal silicide layers 153 and 162b, a stressed material layer 120 is deposited onto the exposed face of the semiconductor structure 100 by using a well-known deposition technique such as, for example, plasma-enhanced chemical vapor deposition (PECVD). Deposition of the stressed material layer 120 may be followed by a UV curing process. The UV curing process, performed at a temperature in the range of 400-500° C., results in an increase of the tensile stress of the stressed material layer 120. The stressed material layer 120 comprises a dielectric material, typically silicon nitride (SiN), having an etch selectivity to a dielectric material layer 130 formed above the semiconductor structure 100 during a later manufacturing stage. Thus, the stressed material layer 120 acts also as an etch stop layer.
An interlayer dielectric material layer 130 is deposited onto the stressed material layer 120. The dielectric layer 130 may comprise any suitable dielectric material, such as, for example, silicon dioxide (SiO2).
The dielectric material layer 130 and the stressed material layer 120 are generally deposited as continuous layers. Thereafter, an etching process, such as reactive ion etching (RIE), is performed on the semiconductor structure 100. Etching may be performed after placing an appropriately patterned etching mask 134 on the surface of the structure 100. Etching is performed in order to form via openings 172 and 174 exposing portions of metal silicide layer 153 contacting the source and drain regions 151 and portions of metal silicide layer 162b contacting gate electrode material 162, respectively.
In a subsequent fabrication step (not shown), via openings 172 and 174 are filled with a high electrical conductivity metal such as tungsten. This allows source and drain regions 151 and gate electrode 160 to be electrically contacted from the outside.
As discussed with reference to FIGS. 1b-1d, the encapsulating portion 144enc and the spacer-0 portion 146sp0 of the spacer structure 140 are formed by performing two consecutive thin-film depositions. More specifically, a first deposition stage 182 including an ALD is performed resulting in formation of the first insulating layer 144, followed by a second deposition stage 184 including an LPCVD and resulting in formation of the second insulating layer 146.
Typically, after performing the first deposition 182, the wafer in which the semiconductor structure 100 is formed is extracted from the first deposition chamber and stored in a carrier, e.g., a front opening universal pod (FOUP). After a variable amount of time, the carriers with the wafer are then transported to the chamber in which the second deposition 184 is to be performed and loaded therein.
This method is unsatisfactory since LPCVD 184 is separated in time from ALD 182 by a variable time interval called “q-time.” The wait time between ALD 182 and LPCVD 184 may have an order of magnitude in the range of approximately 1 hour to 100 hours. In general, the wait time between the two deposition steps may vary depending on tool avail-ability both at the metrology step and at the second LPCVD deposition step.
It has been observed that the thickness of the spacer structure 140 prior to halo and extension implantations critically depends on the q-time elapsing between ALD 182 and LPCVD 184. FIG. 3 shows a graph in which the thicknesses of spacer structures obtained in a series of experiments are plotted as a function of the q-time. The thickness has been obtained as the sum of the thicknesses of the first insulating layer 144 and the second insulating layer 146 shown in FIG. 1c. Circles, triangles and asterisks represent data points obtained with q-times smaller than 6 hours, in the range of 6-48 hours, and greater than 48 hours, respectively.
FIG. 3 clearly shows that the spacer thickness tends to decrease with increasing q-time. The decrease is more pronounced the shorter the q-time is.
One more drawback with the two-stage deposition process described above lies in the fact that carriers or enclosures such as FOUPs, wherein wafers are stored between the first deposition 182 and the second deposition 184 are typically not hermetically sealed. Thus, exposure of the wafers to air results in an oxidation of the surface of the first insulating layer 144 formed by ALD. Surface oxidation of the first insulating layer 144 causes a delay of the subsequent LPCVD growth on the oxidized surface. This results in a further decrease of the overall thickness of the two deposited layers and of the spacer structure.
It is observed that forming spacer structures 140 with a well-defined, repeatable thickness is crucial in order to enable precise halo and/or extension implantations in predetermined regions of the semiconductor layer 102. However, a well-defined, constant q-time may not be achieved in current production lines. Therefore, the effect of thickness reduction with increasing q-time is extremely undesirable.
One solution may be envisaged consisting of increasing the number of cycles of the ALD included in the first deposition stage 182 so as to achieve in one single step the total spacer thickness corresponding to the sum of the thicknesses of layers 144 and 146 shown in FIG. 1c. In this manner, the LPCVD included in the second deposition stage 184 may be omitted altogether. However, this solution may not be pursued, since the resistance to wet etch of a spacer obtained by ALD is usually inferior to that of a spacer resulting from an LPCVD process. In particular, in the case of a spacer comprised of silicon nitride, a nitride grown by ALD turns out to have a higher wet etch rate than a nitride grown by LPCVD, especially when ALD is performed at relatively low temperatures.
In order to solve the problem of the thickness variation of the spacer structure depending on the q-time, a spacer formation process may also be suggested, wherein both growth stages including an ALD and an LPCVD process, respectively, may be performed within the same apparatus. For example, an apparatus with two reaction chambers may be proposed and with a combined loading area. The first of the two chambers could be used for the ALD stage and the second one for the LPCVD. Unfortunately, such an apparatus is not currently available.
One more option would be a combined process including an ALD followed by an LPCVD performed in one single process chamber. However, existing ALD apparatuses may not be used for performing LPCVD of a nitride, as well as existing LPCVD apparatuses may not be used for performing ALD of a nitride.
Thus, in view of the drawbacks and problems illustrated above, it is an object of the present invention to provide a method of forming a spacer structure having a constant, predictable and repeatable thickness.